Logic Design using Verilog | New Approach!

سرفصل های دوره

Advance Digital Design using verilog.

1 - Introduction

1 - Introduction

2 - Adder

2 - HA and FA

3 - Ripple carry adder

3 - Mux

4 - Mux

5 - Gates with mux

4 - Vectored mux

6 - Design Vectored Mux

7 - 42 Priority encoder

8 - 83 priority encoder Solution

5 - Comparator

9 - 1bit comparator

10 - Vectored Comparator

6 - MinMax logic design

11 - MinMax

12 - MinMidMax

13 - MinMidhMidlMin Solution

7 - Vectored Adder

14 - Design Vectored Adder

15 - Next Seconds

8 - Vectored DFF

16 - Design Vectored DFF

17 - 3bit 0 to 7 counter

18 - Mod 5 counter

9 - Design Project

19 - HMS Counter

20 - Mod 4 Mod 5 counter using FSM

10 - Verilog

21 - Introduction to Verilog

11 - Tools Installation

22 - Downloading Modelsim

23 - Installing Modelsim

24 - Running code in edaplayground

12 - Combinational Logic in Verilog

25 - Basic Gates using Verilog

25 - and-gate.zip

25 - run.zip

25 - testbench.zip

26 - HA and FA using basic gates Verilog

26 - fa.zip

26 - ha.zip

26 - run.zip

26 - testbench.zip

27 - Modelling Styles

27 - design.zip

27 - run.zip

27 - testbench.zip

28 - Vectored Mux using Verilog

28 - mux.zip

28 - run.zip

28 - testbench.zip

29 - 42 priority encoder using Verilog

29 - encoder.zip

29 - mux.zip

29 - run.zip

29 - testbench.zip

30 - 83 Priority encoder using verilog Solution

30 - encoder.zip

30 - mux.zip

30 - run.zip

30 - testbench.zip

31 - Vectored comparator using verilog Using waveforms

31 - comp.zip

31 - run.zip

31 - testbench.zip

31 - wave.zip

32 - MinMax using verilog

32 - mm.zip

32 - run.zip

32 - testbench.zip

33 - MinMidMax Solution

33 - mm.zip

33 - mmm.zip

33 - run.zip

33 - testbench.zip

34 - Vectored Adder with small checker logic

34 - adder.zip

34 - run.zip

34 - testbench.zip

35 - Next seconds using verilog

35 - design.zip

35 - run.zip

35 - testbench.zip

13 - Sequential Logic in Verilog

36 - Vectored DFF using Verilog

36 - design.zip

36 - run.zip

36 - testbench.zip

37 - 3bit 0 to 7 counter using verilog

37 - design.zip

37 - run.zip

37 - testbench.zip

38 - Mod 5 counter using verilog

38 - design.zip

38 - run.zip

38 - testbench.zip

14 - HMS Project in verilog

39 - HMS counter part 1

40 - HMS counter part 2

40 - design.zip

40 - run.zip

40 - testbench.zip

15 - Verification

41 - Part 2 and Part 3

16 - To delete

42 - Logic Gates

43 - Mux

44 - Adders

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تولید کننده: Udemy