Fundamentals of Arm architecture(Armv7-A, Armv8-A) – Part.1

سرفصل های دوره

1 - Introduction

1 -Why we need to learn Arm architecture - Part.1

2 -Why we need to learn Arm architecture - Part.2

2 - Introducing Registers

1 -What is the register

2 -How to learn about register

3 - Armv7-A Part1. General-purpose register

1 -Armv7-A Register Overview

2 -Armv7-A banked register R13 mode (Part.1)

3 -Armv7-A banked register R13 mode (Part.2)

4 -Armv7-A banked register R14 mode

4 - Armv7-A Part2. CPSR and SPSRs

1 -CPSR (The Current Program Status Register)

2 -SPSRs (The Special Program Status Register)

3 -How SPSRs are updated (Interrupt)

5 - Armv8-A - Register

1 -Introducing register in Armv8-A

2 -General-purpose registers

3 -Special Registers

4 -ELR ELx - Exception link register

5 -Introducing SPSR ELx register

6 -How is SPSR ELx register updated during generation of exception

6 - Mastering Register with TRACE32 debugging

1 -Armv7-A Identify the general-purpose register

2 -Armv7-A Debugging banked register (Part.1)

3 -Armv7-A Debugging banked register (Part.2)

7 - Armv8-A System registers

1 -Introducing System registers in Armv8-A

2 -Example of system register - HCR EL2

3 -The lowest exception level for system registers

4 -Write or Read the system registers MSR and MRS

8 - Introducing Assembly instruction

1 -What is it challenging to learn about assembly instruction

2 -What can we do using assembly instruction 1. Bringup

3 -What can we do using assembly instruction 2. Develop device driver

4 -What can we do using assembly instruction 3. Improve debugging ability

5 -Basic form of assembly instruction

6 -MOVE instruction

9 - Arithmetic instruction

1 -ADD instruction

2 -ADD instruction (TRACE32 practice)

3 -SUB instruction

4 -SUB instruction (TRACE32 practice)

10 - Logical operation

1 -AND instruction

2 -AND instruction (TRACE32 debugging)

3 -ORR instruction

4 -ORR instruction (TRACE32 debugging)

5 -ORN instruction

6 -BIC instruction

7 -EOR instruction

11 - Bit shift operation

1 -Introducing Bit Shift operation

2 -LSL instruction

3 -LSR instruction

12 - Branch operation

1 -B instruction

2 -BL instruction

3 -BX instruction - Armv7

4 -BLX instruction - Armv7

5 -BX, BLX instruction (TRACE32 Debugging Practice)

6 -BR instruction - Armv8

7 -BLR instruction - Armv8

8 -BR, BLR instruction (TRACE32 Debugging Practice) - Part.1

9 -BR, BLR instruction (TRACE32 Debugging Practice) - Part.2

13 - Conditional branch operation

1 -Introduction to conditional operation

2 -CBZ instruction

3 -CBNZ instruction

4 -TBZ instruction

5 -TBZ instruction (TRACE32 debugging)

6 -TBNZ instruction

7 -TBNZ instruction (TRACE32 debugging)

14 - Exception-generating instruction

1 -SVC instruction

2 -HVC instruction

3 -SMC instruction

15 - Memory Access operation

1 -LDR instruction - Part.1

2 -LDR instruction - Part.2

3 -STR instruction - part.1

4 -STR instruction - part.2

16 - Processor mode(Armv7-A)

1 -User mode

2 -Supervisor mode

3 -IRQ mode and FIQ mode

4 -Abort mode

5 -Undefined mode

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تولید کننده: Udemy