SystemVerilog/UVM for ASIC/SoC Verification Part 2

سرفصل های دوره

Advanced SystemVerilog/UVM Concepts Explained using AMBA-AHB Protocol

1 - SystemVerilog Coverages

1 -SystemVerilog Coverage

2 -Functional coverage and its implementation

3 -Functional coverage-Syntax

2 - SystemVerilog Assertions

1 -SystemVerilog Assertions

3 - Transaction Level Modelling Concepts

1 -TLM Communications

2 -What is TLM & TLM Interfaces

3 -Basic TLM Communication

4 -Put vs Get

5 -FIFOs

6 -Analysis Port

4 - Introduction AHB Protocol

1 -AHB Protocol part 1

2 -AHB Protocol Part 2

3 -Overview of AHB operation

4 -AHB - Simple Transfer

5 -AHB - Transfer with wait states

6 -AHB - Transfer type and Example

5 - Summary of Introduction to UVM and UVM Components

1 -Introduction to UVM & UVM Components

2 -Introduction to UVM & UVM Base

3 -What is UVM

4 -Key Features of UVM

5 -Goal of UVM

6 -UVM Testbench Architecture

6 - Component Configuration and Factory Registration

1 -Setting up the Environment

7 - UVM Phases and Processes

1 -Understanding the UVM Phases

8 - UVM Testbench Architecture

1 -Introduction to UVM Testbench Architecture

2 -Structural Component vs Stimulus generation

3 -Inheritance in UVM

4 -UVM Testbench block diagram and UVM Top

5 -UVM Test

6 -UVM Environment

7 -Universal Verification Components

8 -UVM Agent

9 -Sequencer

10 -Driver

11 -Monitor

12 -Scoreboard

9 - UVM Sequences and Transactions

1 -Introduction to UVM Sequences & Transactions

2 -Sequence Class

3 -Generate Transactions in Sequence Class

4 -User Can Manually Create and Send Item

5 -uvm do macro

6 -uvm rand send macro

7 -uvm create macro

8 -uvm do with macro

9 -uvm do pri macro

10 -uvm do pri with macro

11 -uvm send pri macro

12 -uvm rand send pri macro

13 -uvm rand send pri with macro

14 -Structural Components vs. Stimulus Generation

15 -uvm do macro Interaction Detailed

16 -UVM Inheritance

17 -Sequence Execution Starting a Sequence

18 -UVM Testbench top

19 -start() method in Sequence Class

20 -Sequence Execution Methodologies

21 -Explicit Sequence Execution

22 -Implicit Sequence Execution

23 -UVM Sequencer

24 -UVM Sequencer Example

25 -Driver Sequencer Handshake

26 -How the Handshake works

27 -Virtual Sequence

28 -Virtual Sequencer

29 -Example Virtual Sequencer

30 -Arbitration in UVM Sequencer

10 - UVM Testbench Debugging Techniques

1 -UVM Reporting

11 - AHB based Project Work and Review

1 - AHB Testbench from Scratch.html

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تولید کننده: Udemy