VSD – TCL programming – From novice to expert – Part 2

سرفصل های دوره

The Conclusion

1. Introduction

1. Introduction

2. Introduction to Yosys synthesis tool usage

1. Example of a memory module RTL description

2. Memory functionality and Synthesis using Yosys

3. Components and Gate level netlist description of Snthesized memory

4. Memory Write operation discussed in detail

5. Memory Read operation and TCL scripting agenda

3. Hierarchy check and error handling script creation for Yosys

1. Script to do hierarchy check

2. Demo for hierarchy check script generation

3. Demo for error handling concept in hierarchy check

4. Error handling script for hierarchy check

5. Demo for error handling script

4. Synthesis main file scripting and output file editing

1. Synthesis script creation and demo

2. Need and script to edit yosys output netlist

3. Demo to edit output netlist and Introduction to procs

5. World of Procs

1. Redirect stdout proc and demo of TCL array command

2. set multi cpu usage proc

3. Demo for set multi cpu usage proc

4. read lib and read verilog proc demo

6. read sdc proc - interpret clock generation constraints

1. Read SDC file and replace square brackets by null

2. Evaluate clock period and clock port name from processed SDC

3. Evaluate duty cycle and create clock in opentimer format

4. Demo to convert constraints from SDC format to opentimer format

7. read sdc proc - interpret IO delays and transition constraints

1. Grep clock latency and port name from SDC file

2. Convert set clock latency SDC to opentimer format

3. Demo to convert set clock latency in SDC to arrival time in opentimer

4. Script and demo convert transition and input delay to opentimer format

5. Script and demo to convert output SDC constraints to opentimer format

8. Process bussed ports and configuration file creation

1. Script to expand bussed input ports for arrival time constraints

2. Script and demo to convert all bussed constraints to bit-blasted

3. Opentimer configuration file creation

9. Quality of results (QOR) generation algorithm

1. Script to obtain STA runtime

2. Script to obtain WNS and FEP for reg2out violations

3. Script and demo for instance count, WNS and FEP for setup and hold

4. Script and demo for report formatting

10. Conclusion

1.1 vsdsynth.tar.zip

1. Conclusion and acknowledgements

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