UVM for Verification Part 2 : Projects

سرفصل های دوره

Using UVM for verification of most common RTLs

1. Agenda

1. Course Overview

2. Verification of Combinational Circuit 4-bit Multiplier

1. Multiplier P1

2. Multiplier P2

3. Multiplier P3

4. Design Code.html

5. Verification Environment.html

3. Verification of Sequential Circuit Data Flipflop

1. DFF P1

2. DFF P1

3. DFF P3

4. Design Code.html

5. Verification Code.html

4. Verification of UART

1. Clock Generator for different Baud

2. Verification P1

3. Verification P2

4. Clock Generator Design.html

5. Clock Generator Verification environment.html

6. Understanding UART system

7. UART Clock Generator

8. UART Transmitter

9. UART Receiver

10. System Top

11. Typical Transaction

12. Simple TB code.html

13. Verification Environment P1

14. Verification Environment P2

15. Design Code.html

16. Verification Environment.html

5. Verification of SPI Memory

1. Understanding SPI Controller RTL

2. Understanding SPI Memory

3. Typical Transactions

4. SPI controller P1

5. SPI controller P2

6. Design Code.html

7. Verification Environment.html

8. Understanding Native Transactions

9. Native SPI P1

10. Native SPI P2

11. Design Code Native.html

12. Verification Environment Native.html

6. Verification of I2C Memory

1. Understanding I2C

2. I2C Slave Memory

3. I2C Master Controller

4. Typical Transaction to DUT

5. Verification Environment P1

6. Verification Environment P2

7. Design Code.html

8. Verification Environment.html

7. Veriicantion of APB_RAM

1. Fundamentals

2. Understanding Design

3. Understanding Transactions

4. ABP_RAM P1

5. ABP_RAM P2

6. ABP_RAM P3

7. Design Code.html

8. Verification Environment.html

8. Verification of AXI Memory

1. Understanding AXI Channels

2. Write address Channel

3. Write Data Channel

4. Write Response Channel

5. Single Write Transaction

6. Implementing Write Channel P1

7. Understanding Burst Type P1

8. Understanding Burst Type P2

9. Understanding Burst Type P3

10. Implementing Write Data Channel

11. Implementing Write Response Channel

12. Read Channel

13. Implementing Read Channel

14. Verification Environment P1

15. Verification Environment P2

16. Verification Environment P3

17. Design Code.html

18. Verification Environment.html

9. Understanding usage of Sequence Library

1. Sequence Library P1

2. Sequence Library P2

3. Code.html

10. Understanding TLM Analysis FIFO

1. Understanding TLM FIFO usage

2. Demonstration

3. Code.html

4. Usage of TLM Analysis FIFO P1 Design

5. Usage of TLM Analysis FIFO P1 Verification Env P1

6. Usage of TLM Analysis FIFO P1 Verification Env P2

7. Usage of TLM Analysis FIFO P1 Verification Env P3

8. Design Code.html

9. Verification Environment.html

11. Understanding Virtual Sequencer

1. Virtual Sequencer P1

2. Virtual Sequencer P2

3. DUT

4. Verification Environment P1

5. Verification Environment P2

6. Verification Environment P3

7. Design Code.html

8. Verification Environment.html

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تولید کننده: Udemy-Training