Digital Timing Basics for VLSI Interview & SoC Design

سرفصل های دوره

A VLSI Course on Timing Concepts frequently used in Physical Design (Static Timing Analysis - STA), RTL & Circuit Design

1 - Introduction

1 - Introduction

2 - Understanding Flop Timings

2 - Basic Definitions

3 - Quick Summary

4 - Setup Time & Setup Margin

5 - Hold time & Hold Margin

6 - Clock to Q Delay

3 - Static Timing Foundation

7 - Buffer

8 - Logic Implementation

9 - Physical Implementation

10 - Setup Time Condition in Cycle Path

11 - Hold Time Condition in Cycle Path

12 - Example for Setup & Hold Condition

4 - Problem Solving for Interview

13 - Setup & Hold Margin Computation

14 - Setup Violation

15 - Setup Violation Fix Clock Path Delay

16 - Hold Violation

17 - Hold Violation Fix Data Path Delay

18 - Good Margin but Higher Latency

19 - Latency Reduction with Optimized Design

20 - Design Issues in Real World SoC

5 - Advanced Concepts for Interview Timing Margins

21 - Positive Latch Setup & Hold Time

22 - Negative Latch Setup & Hold Time

23 - Clock Gating Setup & Hold Time

24 - Negative Hold Time for Flop

25 - Negative Setup Time for Flop

6 - Common Misconceptions

26 - Setup Hold Clk2Q and Clock Skew

27 - Hold Margin with Frequency

28 - Setup Margin with Frequency

7 - Frequency vs Voltage in SoC

29 - FV Curve Introduction

30 - FV Curve Explanation

8 - Practical Design Issue1 Multiple Parallel Paths

31 - Multiple Path Problem Statement

32 - Multiple Path Setup Time Analysis

33 - Multiple Path Hold Time Analysis

34 - Multiple Path Summary

9 - Practical Design Issue 2 Max & Min Frequency of Operation

35 - Frequency of Operation

36 - Minimum Frequency of Operation

37 - Maximum Frequency of Operation without Clock Skew

38 - Maximum Frequency of Operation with Clock Skew

10 - Quiz & Next Step

39 - Next Step

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تولید کننده: Udemy-Training