Digital Design from Scratch

سرفصل های دوره

Using VHDL in FPGAs from the ground up

1 - Fundamentals

1 - 11 Introduction

1 - lecture-1-1.pdf

2 - 12 Boolean logic gates binary state and timing diagrams

2 - lecture-1-2.pdf

3 - 13 traffic light example coding Boolean equations

3 - lecture-1-3.pdf

4 - 14 the latch

4 - lecture-1-4.pdf

5 - 15 enabled latches series operations and risingedge pulses

5 - lecture-1-5.pdf

6 - 16 process and conditional statements clocked registers

6 - lecture-1-6.pdf

7 - 17 registertoregister transfers holdsetup time

7 - lecture-1-7.pdf

8 - 18 elsif enabled setreset flop propogation delays

8 - lecture-1-8.pdf

2 - Functional Design Components

9 - 21 binary and hexadecimal numbers

9 - lecture-2-1.pdf

10 - 22 shift registers counters vectors and 1k vs 1K

10 - lecture-2-2.pdf

11 - 23 counter in the traffic light application edge and terminal count detect

11 - lecture-2-3.zip

12 - 24 coding from timing diagrams

12 - lecture-2-4.pdf

13 - 25 introduction to state machines

13 - lecture-2-5.pdf

14 - 26 case statements

14 - lecture-2-6.pdf

15 - 27 state machines case statements and the traffic example

15 - lecture-2-7.pdf

16 - 28 coding the simple traffic state machine

16 - lecture-2-8.pdf

3 - FPGAs VHDL and simulation

17 - 31 introduction to FPGAs

17 - lecture-3-1.pdf

18 - 32 VHDL headon text editors

18 - lecture-3-2.pdf

19 - 33 entities and architectures vector types and VHDL libraries

19 - lecture-3-3.pdf

20 - 34 modular design debounce fallingedge detection

20 - lecture-3-4.pdf

21 - 35 introduction to simulation

21 - lecture-3-5.pdf

22 - 36 simulation testbench creatiing stimulus

22 - lecture-3-6.pdf

23 - 37 introduction to Modelsim constants stalling process statements

23 - lecture-3-7-downloads.zip

24 - 38 using Modelsim

24 - lecture-3-8.pdf

4 - Practical FPGA Elements

25 - 41 single and dualport memories

25 - lecture-4-1.pdf

26 - 42 arrays and while loops

26 - lecture-4-2-downloads.zip

27 - 43 inferred memories coded dualport memory shared bus RAM tristate buffer

27 - lecture-4-3-downloads.zip

28 - 44 FIFOs

28 - lecture-4-4-downloads.zip

29 - 45 Avalon and AXI memorymapped buses

29 - lecture-4-5.pdf

30 - 46 serial interfaces RS232 UARTs

30 - lecture-4-6-downloads.zip

31 - 47 I2C SPI clocks and timing

31 - lecture-4-7.pdf

32 - 48 introduction to DSP

32 - lecture-4-8.pdf

5 - Bonus clock recovery in serial interfaces

33 - Bonus-lecture.pdf

33 - Serial interface clock recovery

139,000 تومان

خرید اشتراک افزودن به سبد خرید

خرید دانلودی فوری

در این روش نیاز به افزودن محصول به سبد خرید و تکمیل اطلاعات نیست و شما پس از وارد کردن ایمیل خود و طی کردن مراحل پرداخت لینک های دریافت محصولات را در ایمیل خود دریافت خواهید کرد.

تولید کننده: Udemy-Training